Pipelined architecture for filter bank based 1-D DWT

A Convolution based parallel and pipelined architecture using MAC Loop Based Filter (MLBF) is proposed in this work. The proposed modification to the MLBF structure produces one output sample for every clock cycle as compared to the MLBF structure which produces two outputs for every four clock cycles. This results in a speed up of 2× which is significant for processing real time signals of long length. Compared to the existing MLBF based 1-D DWT architecture, proposed design uses additional 8 multipliers and 8 adders. The proposed structure is independent of the input size and filter length and performs better than other architectures with same or less area utilization. Generality, scalability, high efficiency of hardware utilization are the other merits of the proposed structure. The architecture is synthesized on Virtex 6 xc6vcx240t-2ff784 FPGA board and can operate at a maximum frequency of 633.43 MHz. The frequency of operation is twice as that of the existing approach.